module ysyx_22040213_pc(
	input clk,
	input rst,

	input to_fs_valid,
	input ID_allow_in,
	input IF_ready_go,

	output IF_allow_in,
	output IF_to_ID_valid,

	input [63:0] dnpc,
	output pc_w_en,
	output reg IF_valid,
	output[63:0] pc	
);
//-------------------if -----------------//
//	reg IF_valid;
	wire cancel = 1'b0;
	reg cancel_next_inst;

	assign IF_allow_in = !IF_valid || (IF_ready_go & ~cancel_next_inst) && ID_allow_in;
	assign IF_to_ID_valid = IF_valid && (IF_ready_go & ~cancel_next_inst);
	
	always @(posedge clk)begin
	  if(rst)begin
	    IF_valid <= 1'b0;
          end else if(IF_allow_in)begin
	    IF_valid <= to_fs_valid;
    	  end else if(cancel && ~IF_allow_in && IF_ready_go)begin
    	    IF_valid <= 1'b0;
    	  end else begin
	  end

	  if(rst)begin
	    cancel_next_inst <= 1'b0;
	  end else if(to_fs_valid && cancel)begin
	    cancel_next_inst <= 1'b1;
	  end else if(cancel && ~IF_allow_in && ~IF_ready_go)begin
	    cancel_next_inst <= 1'b1;
    	  end else if(cancel && ~IF_allow_in && IF_ready_go)begin
	    cancel_next_inst <= 1'b0;
    	  end else begin
    	    cancel_next_inst <= 1'b0;
	  end
	end
	
	assign pc_w_en =  to_fs_valid && IF_allow_in;	
	Reg #(64, 64'h0000000080000000-4) i0 (clk, rst, dnpc, pc, pc_w_en);
endmodule
